• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A forced generation circuit of a line seizing signal in an exchange is provided to forcedly transmit a signal seizing or using a line to a terminal of a caller by sensing whether there is an abnormality in a ring signal. CONSTITUTION: A pulse generator(50) converts a ring signal inputted from a ring signal generator into a pulse signal and outputs the same. A delay unit(60) delays the signal inputted from the pulse generator(50) and outputs the same. A counter(70) counts the signal inputted from the delay unit(60) and outputs signals of a plurality of states. A first AND gate(80) receives the output of the counter(70) and outputs the signal if every inputted signals are a high level. A first flip-flop(62) outputs the signal according to a clock signal upon receipt of the output of the first AND gate(80). A second flip-flop(64) outputs the signal according to a clock signal upon receipt of the output of the first flip-flop(62).
    公开号:KR20020004734A
    申请号:KR1020000038924
    申请日:2000-07-07
    公开日:2002-01-16
    发明作者:박기태
    申请人:서평원；엘지정보통신주식회사；
    IPC主号:
    专利说明:

    Line occupancy signal forced generation circuit of exchange {A GENERATION CIRCUIT OF LINE OCCUPATION SIGNAL FOR EXCHANGE BY COMPULSION}
    [11] The present invention relates to a circuit for forcibly generating a line occupancy signal and transmitting it to a caller when a trouble occurs in a ring signal generation part that calls a callee of an exchange.
    [12] There is a ring signal generating device for indicating that the called party is called in an exchange or a station apparatus for remote transmission. The ring signal generating device outputs a ring signal to the called terminal and outputs a ringback tone signal to the caller. For example, the response state of the called party can be checked.
    [13] Hereinafter, with reference to the accompanying drawings will be described a ring signal generation device of a switch or station apparatus according to the prior art.
    [14] 1 is a functional block diagram of a general exchange system, which is attached to explain a ring signal generator of a switch according to the prior art.
    [15] Referring to the accompanying drawings, the exchange system, the terminal 10 of the subscriber A to be called,
    [16] A ring signal generator 35 which directly connects to the terminal 10 and connects a called party to a called side exchange which is directly connected, and generates a ring signal confirming that the called party is called. And the call side exchange A 20,
    [17] The called side, which is connected by the calling side exchange A 20, connects a path with the called party, and also includes a ring signal generator 30 which generates a ring signal confirming that the called party is called. Exchanger B (25),
    [18] The call is exchanged by the exchange B (25) and the terminal 15 of the subscriber B which recognizes that the call is received by receiving a call ring signal.
    [19] The ring signal generator of the prior art by the exchange of the above general configuration will be described.
    [20] When the subscriber to be called makes a call using the terminal A 10, the caller establishes a path at the exchange A 20 so that the called party is connected to the connected exchange B 25. Switch B (25) connected by means of setting a path with the called terminal B (15), then controlling the ring signal generator (30) to output a ring signal to the terminal B (15). At the same time, by generating a ring-back tone signal and applying it to the terminal A 10 through the exchange A 20, the caller confirms that the called party is called and responds to the called party's response. I will wait.
    [21] However, in the prior art as described above, when a failure occurs in the ring signal generator 30 of the called-side exchanger B 25, the called terminal B 15 does not hear the ring signal that the called terminal has been called. At the same time, since no ringback tone signal is generated, i.e., there is no response at all, it is determined that the called terminal B 10 is in communication by occupying the line or that the called signal is received. There is a problem that it is not possible to determine whether a call is in a waiting state, and there is a problem that a user's reliability of the exchange system as described above is deteriorated.
    [22] SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit which detects an abnormality of a ring signal and forcibly transmits a line occupied or busy signal to a caller terminal when a ring signal generation part of a called side exchange occurs.
    [23] In order to achieve the above object, the present invention is a ring signal generation unit of the switch, a pulse generator for processing the ring signal input from the ring signal generation unit to convert the pulse signal into a pulse signal, the pulse generation A delay unit for delaying and outputting a signal input from the unit, a counter for counting the signal input from the delay unit, and outputting a signal of a plurality of states; In this case, the first AND gate outputting a signal, the first flip-flop outputting the output of the first AND gate by a clock signal applied thereto, and the clock signal receiving and applying the output of the first flip-flop A second flip-flop output by the second flip-flop, a third flip-flop outputting the output of the second flip-flop by a clock signal applied thereto, and The group has a feature consisting of a second AND gate for outputting a received signal is applied to a high-level busy signal from both the first AND gate and the first to third flip-flops.
    [1] 1 is a functional block diagram of a general exchange system,
    [2] 2 is a functional block diagram of a line occupancy signal forced generation circuit according to the present invention;
    [3] 3 is a detailed circuit diagram of a pulse generator according to the present invention.
    [4] ** Explanation of symbols on the main parts of the drawing **
    [5] 10,15 terminal 20,25 switchboard
    [6] 30,35: ring signal generator 50: pulse generator
    [7] 51,54,55,57: resistor 52,53: diode
    [8] 56 regulator 58 clamping part
    [9] 60: delay unit 70: counter
    [10] 80,85: ANDGATE 62,64,66: flip-flop
    [24] Hereinafter, a line occupancy signal forced generation circuit of an exchange according to the present invention will be described with reference to the accompanying drawings.
    [25] 2 is a functional block diagram of a line occupancy signal forced generation circuit according to the present invention, and FIG. 3 is a detailed circuit diagram of a pulse generator according to the present invention.
    [26] Referring to the accompanying drawings, the circuit occupying signal generation circuit of the switch according to the present invention, the input resistor (51) for detecting the voltage of the applied ring (Ring) signal;
    [27] A first diode 52 for half-wave rectifying the ring signal applied through the input resistor 51;
    [28] A clamping unit 58 for blocking the half-wave rectified ring signal by the first diode 52 below a predetermined level;
    [29] A regulator 56 for shaping a signal output from the clamping unit 58 into a predetermined shape;
    [30] A pulse generator 50 for converting and outputting an input ring signal into a pulse signal by forming a pull-up resistor 57 for applying a signal output from the regulator 56 to an output terminal;
    [31] A delay unit 60 for delaying and outputting a signal input from the pulse generator 50 for a predetermined time;
    [32] A counter 70 for counting signals input from the delay unit 60 and outputting signals in four states;
    [33] A first end gate 80 which receives four state output signals of the counter 70 and outputs a high level signal when the input signals are all high level '1';
    [34] A first flip-flop 62 outputting the output of the first AND gate 80 by a second clock signal CLK2 applied thereto;
    [35] A second flip-flop 64 that receives the output of the first flip-flop 62 and outputs it by a second clock signal CLK2 applied thereto;
    [36] A third flip-flop 66 which receives the output of the second flip-flop 64 and outputs it by the second clock signal CLK2 applied thereto;
    [37] The second AND gate 85 receives a high level signal from both the first AND gate 80 and the first to third flip-flops 62, 64, and 66, and outputs a busy signal. do.
    [38] Hereinafter, with reference to the accompanying drawings will be described in detail the circuit occupancy signal generation circuit of the switch according to the present invention.
    [39] When the called terminal B (15) is called by the user of the terminal A (10), the switch B (25) connected to the switch A (20) controls the ring signal generator 30 to control the called terminal. To B 15, a ringing signal indicating that an incoming signal has arrived is output, and at the same time, a ringback tone signal is generated and applied to terminal A 10 via exchange A 20.
    [40] However, when the ring generator 30 fails to generate the call ring signal and the ring back tone signal, the circuit occupying signal generation circuit according to the present invention operates.
    [41] The line occupancy signal forced generation circuit according to the present invention monitors the ring signal output from the ring signal generator 30 by the input resistance 51 of the pulse generator 50.
    [42] Since the ring ring signal normally generated by the ring signal generator 30 is a sine wave signal of ± 80 V as shown in FIG. 3, a half wave is generated by the first diode 52. ) Is detected or rectified.
    [43] The ring signal rectified by the first diode 52 only by a half wave is less than or equal to a predetermined voltage, that is, 5V or less by the second diode 53 and the resistors 54 and 55 of the clamping unit 58. The signal is blocked or suppressed by the signal, and is applied to the regulator 56, shaped into a pulse, and output by a pull-up resistor 57 as a zero crossing signal (ZCS) of 50 ms periods.
    [44] When a ring signal is normally applied to the pulse generator 50, a ZCS signal is output as shown in FIG. 3, and when a failure occurs in the ring signal generator 30, A ZCS signal with a low level is output.
    [45] The delay unit 60 receiving the ZCS signal from the pulse generator 50 is delayed for a predetermined time by the first clock signal CLK 1 and then applied to the counter 70.
    [46] When the low level signal is input, the counter 70 starts counting by the first clock CLK 1. For example, the counter 70 outputs signals in four states. In the case where all four output signals of) are high level, the first AND gate 80 outputs the output at the high level.
    [47] In more detail, when the ring signal is normally generated in the ring signal generator 30, the counter 70 does not count because the high and low level signals are repeated. If a failure occurs in 30 and no ring signal is generated, the low signal is continuously input to the counter 70, so that the counter 70 starts counting and the four different states. Will output the signal of.
    [48] As described above, when a failure occurs in the ring signal generation unit 30, a continuous low level signal is applied to the counter 70, and four different signals are input to the first end gate 80. The first AND gate 80 outputs a high level signal and is applied to the first flip-flop 62.
    [49] As an example, the first flip-flop 62 receives a second clock signal CLK 2 having a 16 msec period and is applied to the second flip-flop 64 after being delayed for 16 msec. The second flip-flop 64 is delayed for another 16 msec by the second clock signal CLK 2 and then output to the third flip-flop 66.
    [50] The third flip-flop 66 is also output after being delayed for 16 msec by the second clock signal CLK 2.
    [51] In more detail, the signal output from the first and gate 80 is output by the first to third flip-flops 62, 64 and 66 after being delayed for 54 msec.
    [52] The output signals of the first and gate 80 and the first to third flip-flops 62, 64, and 66 are input to the second and gate 85 and are in a high state when all input signals are high level. Busy signal, that is, a signal that the callee's line is occupied is forcibly generated.
    [53] The Busy signal is output to the terminal A 10 via the exchange A 20 by the exchange B 25 and at the same time, outputs a failure alarm signal corresponding to the corresponding maintenance unit.
    [54] Therefore, the user of the terminal A 10 hears the busy signal, determines that the called party is using the terminal B 15, that is, the line is occupied and is in use, and terminates the call, thus not answering. By reducing the waiting time, the operator can easily perform maintenance by checking the alarm signal.
    [55] The configuration according to the present invention provides a caller's waiting time by forcibly generating and transmitting a signal that the line is occupied and in use by a caller when a ring signal generation part of the exchange warns the called state of the called party. As to shorten, there is an effect of improving the convenience of the user.
    [56] In addition, by reducing the waiting time of the user indefinitely due to the non-responsiveness of the called party, it reduces the load of the exchange and serves as an exchange function for other users, thereby improving the social utility and improving the reliability of the exchange. Use effect
    权利要求:
    Claims (2)
    [1" claim-type="Currently amended] In the ring signal generator of the exchange,
    A pulse generator which processes the ring signal input from the ring signal generator and converts the ring signal into a pulse signal;
    A delay unit for delaying and outputting a signal input from the pulse generator;
    A counter for counting a signal input from the delay unit and outputting a signal of a plurality of states;
    A first AND gate which receives an output of the counter and outputs a signal when the input signals are all at a high level;
    A first flip-flop configured to receive an output of the first AND gate in response to a clock signal applied thereto;
    A second flip-flop that receives the output of the first flip-flop and outputs it by a clock signal applied thereto;
    A third flip-flop that receives the output of the second flip-flop and outputs it by a clock signal applied thereto;
    And a second AND gate configured to receive a high level signal from both the first AND gate and the first to third flip-flops, and to output a busy signal.
    [2" claim-type="Currently amended] According to claim 1,
    The pulse generator may include an input resistor for detecting a voltage of an applied ring signal;
    A first diode for half-wave rectifying the ring signal applied through the input resistance;
    A clamping unit for blocking the half-wave rectified ring signal by the first diode below a predetermined level;
    A regulator for shaping the signal output from the clamping unit into a predetermined shape;
    And a pull-up resistor for applying a signal output from the regulator to an output terminal.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-07-07|Application filed by 서평원, 엘지정보통신주식회사
    2000-07-07|Priority to KR1020000038924A
    2002-01-16|Publication of KR20020004734A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000038924A|KR20020004734A|2000-07-07|2000-07-07|A generation circuit of line occupation signal for exchange by compulsion|
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